An important consideration in the design of an electronic timepiece is the method by which the running rate of the timepiece is to be adjusted and measured, at the time of manufacture or at some subsequent time. The most commonly used method hitherto has been to provide a trimmer capacitor in the standard frequency quartz crystal oscillator circuit of the timepiece, and to adjust this trimmer capacitor in order to vary the output frequency from the standard frequency oscillator, to thereby modify the running rate of the timepiece. This method has the disadvantage that, since the capacity value of the trimmer must remain very stable over a long period of time, in order to ensure stability of the running rate of the timepiece, the trimmer capacitor is a relatively expensive component. An alternative method which has been proposed for adjusting the running rate of an electronic timepiece has been to vary the frequency division ratio of the frequency divider circuit of the timepiece, so that the frequency of a unit time signal produced by the frequency divider circuit is correct. The necessity for adjusting the frequency of the standard frequency quartz crystal oscillator circuit of the timepiece is thereby obviated. The most simple and economical method of adjusting the frequency division ratio of the frequency divider in an electronic timepiece is to select a number of signals of different frequency produced by the frequency divider circuit and to combine these to produce a running rate correction signal of suitable frequency. This running rate correction signal is then added aperiodically in frequency to the output signal from the standard frequency oscillator of the timepiece, and the resultant signal is input to the frequency divider circuit.
Such a method would appear to offer various advantages over the use of a trimmer capacitor for running rate adjustment. However, up to the present, such a method of running rate adjustment has not come into widespread use. The principal reason for this is that, since the signal which is input to the frequency divider (and hence, signals subsequently produced by the frequency divider) are aperiodic, it is extremely difficult to measure the running rate of the timepiece quickly and easily. In the case of an electronic timepiece of conventional design, for example, in which the signals applied to the timekeeping and display section of the timepiece are periodic, it is possible to measure the running rate of the timepiece rapidly and easily while the timepiece is in a completely assembled and operating state. This can be accomplished, for example, by means of an external monitoring device such as is disclosed in U.S. Pat. No. 3,946,591 by Yanagawa et al. This device includes a sensor which is capacitatively coupled to the electro-optical display device of an electronic timepiece by being brought into proximity with the timepiece dial, and which detects the frequency of a modulation signal applied to electrodes of the electro-optical display. Since this modulation signal frequency is a known submultiple of the frequency of the standard frequency oscillator of the timepiece, the actual running rate of the timepiece can be readily derived from the sensor output signal. Such a method cannot be applied to a timepiece in which the modulation signal frequency is aperiodically modified, due to the use of variable frequency division as discussed above, since it would be necessary to monitor the average modulation signal frequency over an excessively long time period in order to attain any accuracy in estimating the actual effective running rate of the timepiece. This is due to the fact that the aperiodic frequency correction is conducted only relatively infrequently, corresponding to correction by a few seconds per day or per week, for example.
With the present invention, the above disadvantages of utilizing an aperiodic frequency addition method of timepiece running rate correction are eliminated. This is achieved by providing means whereby the aperiodic frequency addition process can be inhibited, by actuation of an external operating member, so that signals produced by the frequency divider circuit of the timepiece are all periodic, and are integral multiples of the frequency of the standard frequency oscillator output signal. In addition, the present invention enables the actual amount of rate correction performed by aperiodic frequency addition of a running rate correction signal to be derived, either by direct display on the timepiece, or by means of an external monitoring device.